Ramakumar Mayil Dilli Babu
Senior Staff Hardware Engineer
REF DES — U1
Professional summary
Senior Staff Hardware Engineer with 21+ years of continuous experience architecting mission-critical hardware systems spanning data-center and AI networking, aerospace, medical devices, and telecommunications infrastructure. Named co-inventor on a granted, internationally extended U.S. patent, independently cited as prior art by an unrelated third-party filing. Track record of technical ownership at organizations including Honeywell Aerospace, Qualcomm, Siemens Healthineers / Varian Medical Systems, GM / Cruise Automation, Olympus, Cisco, and Celestica.
AI/ML networking systems on custom 800G/1.6T ASICs for hyperscale data center infrastructure.
ASIC & PCB architecture, signal & power integrity, high-speed interconnects (DDR, PCIe, USB, SERDES).
Avionics, radiotherapy & medical devices, autonomous vehicles, network security, hyperscale AI compute.
DO-160 / RTCA, IEC 60601-1-2, USB-IF, CPRI qualification and compliance testing.
Patent
Standoff for Circuit Board Having Temperature-Variable Electrical Element
A temperature-variable standoff — the structural spacer mounting a PCB within its enclosure — with an integrated heating element, solving extreme-temperature reliability challenges in avionics electronics. Performed the thermal simulation and validation analysis (Mentor Graphics FloTHERM) that proved the design brought the SIM-card area from –55°C to –20°C in ~260 seconds at 8.5W, within the required 8-minute target and on par with the conventional resistor-based approach.
Experience
- Architecting AI/ML networking systems on custom 800G/1.6T ASICs for next-gen AI data center infrastructure.
- Leading DC-SCM (Data Center Secure Control Module) design — modular, standardized management hardware.
- High-speed interfaces: DDR5, 100GbE+ Ethernet, PCIe Gen5+, 56G+ SERDES-class interconnects.
- Board-level design, verification, and calibration for TrueBeam™ radiotherapy control system boards.
- Root-cause resolution of two production defects, including a 10-channel ion chamber dosimetry issue.
- Formal test-plan authorship (BGM Controller, RFSPS) under IEC 60601-1-2 compliance.
- Technical program management + hardware design for Palo Alto Networks NGFW platforms.
- Full hardware lifecycle for Olympus EVIS X1 ScopeGuide 3D endoscope navigation system.
- Primary Compute Board development for Cruise Automation (GM) autonomous vehicle platform.
- System architecture and full design lifecycle for automotive connectivity control units.
- Named co-inventor, US Patent 11,324,110 B2 — temperature-variable circuit-board standoff.
- End-to-end hardware development and DO-160 qualification for the Satellite Data Unit platform.
- Formal design reviewer with sign-off authority during design release / PDR process.
- Solution release ownership for WiFi access point and modem test platforms across 2G/5G variants.
- Fabric and Spine Card design for the Cisco Nexus 7000 data-center platform, 1/10/40/100 GbE.
- LTE–3GPP radio-head digital/RF board platform on Xilinx Virtex-5; Module Lead, team of 5.
- Pre-/post-silicon board design & validation for PCIe-to-USB and USB-to-Serial controller ASICs.
Education & certifications
Bachelor of Engineering, Electronics & Communication Engineering
NIT Trichy (fmr. Regional Engineering College, Tiruchirappalli) · 1996–1999
Affiliated with Bharathidasan University. Institute of National Importance under the NITSER Act, 2007.
Diploma, Electronics & Communication Engineering
State Board of Technical Education and Training, Tamil Nadu · 1990–1993
Passed First Class, April 1993.
- 2018Design for Six Sigma (DFSS) Hardware — Honeywell, applied to ASIC interposer design.
- 2000System Design using Hardware Description Languages — NIT Trichy, Grade A.
- 2021Basics of Geographical Information System — IIRS / ISRO, Dept. of Space.
- 2025Gen AI 101 — Assessment — HCLTech internal certification.